The development of nanofabrication techniques for creating high aspect ratio (∼50:1) sub-10 nm silicon nanowires (SiNWs) with smooth, uniform, and straight vertical sidewalls using an inductively coupled plasma (ICP) etching process at 20 °C is reported. In particular, to improve the quality and flexibility of the pattern transfer process for high aspect ratio SiNWs, hydrogen silsesquioxane, a high-resolution, inorganic, negative-tone resist for electron-beam lithography has been used as both the resist for defining sub-10 nm patterns and the hard mask for etching the underneath silicon material. The effects of SF6/C4F8 gas flow rates, chamber pressure, platen power and ICP power on the etch rate, selectivity, and sidewall profile are investigated. To minimize plasma-induced sidewall damage, moderate plasma excitation power (ICP power of 600 W) and low ion energy (platen power of 6-12 W) were used. Using the optimized etch process at room temperature (20 °C), the authors have successfully fabricated sub-10 nm SiNWs, which have smooth vertical sidewall profile and aspect ratios up to ∼50:1. This optimized etch combined with a controlled thermal oxidation allows the realization of consistent, reproducible, and reliable SiNW devices with nominal widths from 100 nm down to sub-5 nm in silicon on top of SiO2 fabricated on silicon on insulator substrates. © 2012 American Vacuum Society.

Nanofabrication of high aspect ratio (∼50:1) sub-10 nm silicon nanowires using inductively coupled plasma etching

VELHA, PHILIPPE;
2012-01-01

Abstract

The development of nanofabrication techniques for creating high aspect ratio (∼50:1) sub-10 nm silicon nanowires (SiNWs) with smooth, uniform, and straight vertical sidewalls using an inductively coupled plasma (ICP) etching process at 20 °C is reported. In particular, to improve the quality and flexibility of the pattern transfer process for high aspect ratio SiNWs, hydrogen silsesquioxane, a high-resolution, inorganic, negative-tone resist for electron-beam lithography has been used as both the resist for defining sub-10 nm patterns and the hard mask for etching the underneath silicon material. The effects of SF6/C4F8 gas flow rates, chamber pressure, platen power and ICP power on the etch rate, selectivity, and sidewall profile are investigated. To minimize plasma-induced sidewall damage, moderate plasma excitation power (ICP power of 600 W) and low ion energy (platen power of 6-12 W) were used. Using the optimized etch process at room temperature (20 °C), the authors have successfully fabricated sub-10 nm SiNWs, which have smooth vertical sidewall profile and aspect ratios up to ∼50:1. This optimized etch combined with a controlled thermal oxidation allows the realization of consistent, reproducible, and reliable SiNW devices with nominal widths from 100 nm down to sub-5 nm in silicon on top of SiO2 fabricated on silicon on insulator substrates. © 2012 American Vacuum Society.
2012
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11382/516870
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