PAGANI, MARCO

PAGANI, MARCO  

Istituto di Telecomunicazioni, Informatica e Fotonica  

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Risultati 1 - 11 di 11 (tempo di esecuzione: 0.011 secondi).
Titolo Data di pubblicazione Autore(i) File
A bandwidth reservation mechanism for axi-based hardware accelerators on FPGAs 1-gen-2019 Pagani, M.; Rossi, E.; Biondi, A.; Marinoni, M.; Lipari, G.; Buttazzo, G.
A Framework for Supporting Real-Time Applications on Dynamic Reconfigurable FPGAs 1-gen-2017 Biondi, Alessandro; Balsini, Alessio; Pagani, Marco; Rossi, Enrico; Marinoni, Mauro; Buttazzo, Giorgio Carlo
A Linux-based support for developing real-time applications on heterogeneous platforms with dynamic FPGA reconfiguration 1-gen-2022 Pagani, M.; Biondi, A.; Marinoni, M.; Molinari, L.; Lipari, G.; Buttazzo, G.
A Linux-based support for developing real-time applications on heterogeneous platforms with dynamic FPGA reconfiguration 1-gen-2017 Pagani, Marco; Balsini, Alessio; Biondi, Alessandro; Marinoni, Mauro; Buttazzo, Giorgio
ARTE: Arduino real-time extension for programming multitasking applications 1-gen-2016 Buonocunto, Pasquale; Biondi, Alessandro; Pagani, Marco; Marinoni, Mauro; Buttazzo, Giorgio Carlo
ARTe: Providing real-time multitasking to Arduino 1-gen-2022 Restuccia, F.; Pagani, M.; Mascitti, A.; Barrow, M.; Marinoni, M.; Biondi, A.; Buttazzo, G.; Kastner, R.
Automating the design flow under dynamic partial reconfiguration for hardware-software co-design in FPGA SoC 1-gen-2021 Seyoum, Biruk; Pagani, Marco; Biondi, Alessandro; Buttazzo, Giorgio
Bounding Memory Access Times in Multi-Accelerator Architectures on FPGA SoCs 1-gen-2023 Restuccia, Francesco; Pagani, Marco; Biondi, Alessandro; Marinoni, Mauro; Buttazzo, Giorgio
Is your bus arbiter really fair? Restoring fairness in axi interconnects for FPGA SOCs 1-gen-2019 Restuccia, Francesco; Pagani, M.; Biondi, A.; Marinoni, M.; Buttazzo, G.
Modeling and analysis of bus contention for hardware accelerators in FPGA SoCs 1-gen-2020 Restuccia, F.; Pagani, M.; Biondi, A.; Marinoni, M.; Buttazzo, G.
Spatio-Temporal Optimization of Deep Neural Networks for Reconfigurable FPGA SoCs 1-gen-2020 Seyoum, Biruk B.; Pagani, Marco; Biondi, Alessandro; Balleri, Sara; Buttazzo, Giorgio