SEYOUM, BIRUK BELAY
SEYOUM, BIRUK BELAY
Istituto di Telecomunicazioni, Informatica e Fotonica
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Automating the design flow under dynamic partial reconfiguration for hardware-software co-design in FPGA SoC
2021-01-01 Seyoum, Biruk; Pagani, Marco; Biondi, Alessandro; Buttazzo, Giorgio
Flora: Floorplan optimizer for reconfigurable areas in FPGAs
2019-01-01 Seyoum, B. B.; Biondi, A.; Buttazzo, G. C.
Spatio-Temporal Optimization of Deep Neural Networks for Reconfigurable FPGA SoCs
2020-01-01 Seyoum, Biruk B.; Pagani, Marco; Biondi, Alessandro; Balleri, Sara; Buttazzo, Giorgio
| Titolo | Data di pubblicazione | Autore(i) | File |
|---|---|---|---|
| Automating the design flow under dynamic partial reconfiguration for hardware-software co-design in FPGA SoC | 1-gen-2021 | Seyoum, Biruk; Pagani, Marco; Biondi, Alessandro; Buttazzo, Giorgio | |
| Flora: Floorplan optimizer for reconfigurable areas in FPGAs | 1-gen-2019 | Seyoum, B. B.; Biondi, A.; Buttazzo, G. C. | |
| Spatio-Temporal Optimization of Deep Neural Networks for Reconfigurable FPGA SoCs | 1-gen-2020 | Seyoum, Biruk B.; Pagani, Marco; Biondi, Alessandro; Balleri, Sara; Buttazzo, Giorgio |